1. Field of the Invention
The present invention relates to a metal-oxide semiconductor field effect transistor which can be made extremely small in size and is suitable for application to LSI (large-scale integration) circuit technology, and relates to methods of manufacturing such a transistor.
2. Description of the Related Art
In order to produce metal-oxide semiconductor field effect transistors (abbreviated in the following to MOS FETs) which are extremely small in size and hence have a very short channel length, it is necessary to adopt countermeasures against various problems which arise as a result of the size reduction and in particular as a result of channel length reduction. One of these problems is that during operation with a voltage applied to the gate electrode, a very high concentration of electric field is produced within the transistor at the drain pinchoff region. This results in hot-electron emission in that region, which causes problems including degradation of the current drive capability of the transistor, etc. For brevity of description, an NPN MOS transistor configuration will be assumed in the following, although the remarks are equally applicable to a PNP transistor. In the conventional form of such a transistor, the drain and source regions are formed as respective highly doped n-type regions in a p-type semiconductor substrate. Proposals have been made in the prior art for reducing the aforementioned problems which result from MOS FET miniaturization, by forming respective lightly doped n-type source and drain diffusion regions which adjoin the actual (i.e. highly doped) source and drain diffusion regions and which extend into the channel region. In this way the high electric field that is developed in the drain diffusion region of a conventional MOS FET can be spread into the lightly doped n-type diffusion region, and hence the peak value of that electric field is reduced, so that the problems described above can be alleviated. A prior art example of such a structure, called the LDD (lightly doped drain) MOS FET, is described in the IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, August 1980, pages 1359 to 1367. Another prior art example of such a structure is the Inverse-T Gate structure MOS FET (referred to in the following as the inverse-TMOS FET) which is described in the IEDM Technical Digest, 1986, pages 742 to 745.
FIGS. 1 and 2 are respective cross-sectional views of the LDD transistor and the Inverse-TMOS transistor. As used herein, the term "cross-sectional view" of a MOS FET structure refers to a cross-section which is perpendicular to the substrate major planes, and passes centrally through the drain and source diffusion regions. In each of FIGS. 1 and 2, numeral 1 denotes a p-type Si substrate, 2 denotes an electrically insulating film, and 3 denotes highly doped n-type diffusion regions which constitute the drain and source diffusion regions. (It will be assumed that each of the various MOS FET structures described herein is symmetrical, so that for example either of the regions 3 shown in FIG. 1 could function as the drain diffusion region.) Numeral 4 denotes respective lightly doped n-type diffusion regions formed in the semiconductor substrate 1, each of which extends from one of the highly doped n-type diffusion regions 3, into the channel region as shown.
With the prior art LDD MOS FET of FIG. 1, when a high voltage is applied between the source and drain diffusion regions (i.e. each formed of one of the regions 3 together with one region 4), the depletion layer will extend through the regions 4, so that the peak value of the high electric field in the drain region will be reduced, and hence an improvement can be achieved with regard to hot-electron emission and resultant degradation of transistor performance.
With the prior art Inverse-TMOS transistor shown in FIG. 2, when a high voltage is applied between the source and drain diffusion regions, similar effects are obtained to those described above for the LDD transistor, although the Inverse-TMOS structure is described as providing an even greater improvement than is provided by the LDD structure. In addition, the shape of the gate electrode 5a of the Inverse-TMOS structure enables parasitic resistance due to depletion within the n-type lightly doped drain diffusion region 4 to be suppressed.
With such a prior art type of LDD or Inverse-TMOS FET, when a voltage is applied to the gate electrode 5a, a current can flow between the highly doped n-type drain and source diffusion regions 3, whereas when no voltage is applied to the gate electrode 5a, no current can flow between the drain and source diffusion regions. Thus such a device can operate as a MOS FET switch.
However with the prior art LDD MOS FET of FIG. 1, the following problems arise:
(1) Referring to FIG. 3, diagram (a) is a partial cross-sectional view of the LDD MOS FET of FIG. 1, focussed on the drain diffusion region, while diagram (b) is a diagram in which distances along the horizontal axis corresponds to those of diagram (a) and which shows the distribution of electric field in the structure of diagram (a). When a high voltage is applied between the source and drain diffusion regions 3, then due to the fact that the gate electrode 5a is coupled through a very thin layer of the oxide film to the lightly doped drain diffusion region 4 as shown in diagram (a), a high value of electic field is produced within that diffusion region 4 at a position immediately below the outer end of the gate electrode 5a, due to the vertical and horizontal components of the electric field at that position. That very high level of electric field causes hot-electron emission, resulting in various problems as described hereinabove.
(2) Due to the position at which that very high value of electric field is produced, i.e. immediately adjacent to the outer end of the gate electrode 5a, the hot electrons will be readily trapped in the thick side wall formed of oxide film which covers that end portion of the gate electrode. This trapping of hot electrons results in a substantial increase in the rate of degradation of the transistor.
(3) Since depletion will readily occur within the lightly doped diffusion region 4, this constitutes a source of parasitic resistance.
Referring to FIG. 4, diagram (a) is a partial cross-sectional view of the prior art Inverse-TMOS FET of FIG. 2, focussed on the drain diffusion region, while diagram (b) is a diagram in which distances along the horizontal axis corresponds to those of diagram (a) and which shows the distribution of electric field in the structure of diagram (a). With such a structure, the following problems arise:
(1) Due to the fact that the lightly doped drain diffusion region 4 is completely covered by the gate electrode 5a, while separated therefrom by a thin oxide film, the stray capacitance between drain and gate is high, which results in problems such as increased delay time and increased power consumption.
(2) As shown in the electric field diagram (b), the vertical component of electric field within the lightly doped drain diffusion region 4 is increased due to the action of the gate electrode 5a, and when a voltage is applied to the gate electrode 5a for setting the transistor in the OFF state, with a high voltage being applied to the drain diffusion region, then inter-band tunnelling will occur, which results in a drain leakage current, i.e. resulting in gate diode leakage being produced.
Thus, both of these prior art types of MOS FET which attempt to prevent deterioration of performance in spite of miniaturization of the MOS FET structure, by the addition of lightly doped n-type diffusion regions at the drain and source diffusion regions, have respective disadvantages.